Issues

• NVIC resumes a deep-sleep-halted SysTick only for an external IRQ line

  renode/renode#1079 · Filter by author mananni-silabs opened on Nov 12, 2026
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• Caliptra_HMAC: block read from the KeyVault is not padded

  renode/renode#1077 · Filter by author marekvi95 opened on Nov 10, 2026

• Caliptra_KeyVault: KEY_CTRL.last_dword holds the entry length instead of the offset of the last dword

  renode/renode#1076 · Filter by author marekvi95 opened on Nov 10, 2026

• STM32_FDCAN: PSR.EW polarity is inverted — the flag is set at reset while both error counters are zero

  renode/renode#1075 · Filter by author n0shimad122-creator opened on Nov 10, 2026

• stm32l552.repl: NVIC priorityMask should be 0xE0 (3 implemented priority bits), not 0xF0

  renode/renode#1074 · Filter by author n0shimad122-creator opened on Nov 10, 2026

• Cortex-A53 in AArch32 uses the AArch64 MMU walker

  renode/renode#1073 · Filter by author iMoD1998 opened on Nov 9, 2026

• Cortex-A9 crashes on MMU translation fault instead of raising an abort

  renode/renode#1072 · Filter by author iMoD1998 opened on Nov 9, 2026

• STM32H7_ADC only has 19 channels instead of 20. Converting channel index 19 crashes Renode

  renode/renode#1071 · Filter by author Julian-Rederle opened on Nov 9, 2026

• Signed 8/16-bit NEON left-shift helpers invoke C undefined behavior

  renode/renode#1070 · Filter by author canxin121 opened on Nov 6, 2026

• AArch64 FP64-to-FP16 conversion bypasses required rounding and exceptions

  renode/renode#1069 · Filter by author canxin121 opened on Nov 6, 2026

• A32 tiny FP32-to-FP16 inputs ignore directed rounding to minimum subnormal

  renode/renode#1068 · Filter by author canxin121 opened on Nov 6, 2026

• A32 IEEE FP16 NaN conversion loses sign/payload or fails to quiet NaN

  renode/renode#1067 · Filter by author canxin121 opened on Nov 6, 2026

• A32 IEEE FP16 conversion returns infinity for every overflow rounding mode

  renode/renode#1066 · Filter by author canxin121 opened on Nov 6, 2026

• A32 AHP half conversion raises extra Underflow/Inexact on finite overflow

  renode/renode#1065 · Filter by author canxin121 opened on Nov 6, 2026

• A32 AHP FP32-to-FP16 NaN conversion fails to raise Invalid Operation

  renode/renode#1064 · Filter by author canxin121 opened on Nov 6, 2026

• Cortex-A15 VFP feature flags omit required VFP/VFP3 and expose missing CPACR checks

  renode/renode#1063 · Filter by author canxin121 opened on Nov 6, 2026

• stm32f746.repl: timers clocked at 10 MHz, missing UART4/5/7/8, IWDG and CRC, RAM size 384 KiB instead of 320 KiB

  renode/renode#1062 · Filter by author philippecottier opened on Nov 4, 2026

• STM32SPI (F7 series): 16-bit write to DR in 8-bit frame mode sends one byte instead of two (data packing)

  renode/renode#1061 · Filter by author philippecottier opened on Nov 4, 2026

• A32 UASX/USAX produce incorrect GE flags for unsigned halfword lanes

  renode/renode#1058 · Filter by author canxin121 opened on Nov 2, 2026

• A32 VCVT to unsigned fixed-point incorrectly adds IXC for an invalid negative input

  renode/renode#1057 · Filter by author canxin121 opened on Nov 2, 2026

• Renode spuriously sets FPSCR.OFC for AArch32 vector fixed-point conversion

  renode/renode#1056 · Filter by author canxin121 opened on Nov 2, 2026

• A32 FP32-to-FP16 conversion reports incorrect FPSCR exception flags

  renode/renode#1055 · Filter by author canxin121 opened on Nov 2, 2026

• A32 UHSUB8 computes halving differences across byte lanes

  renode/renode#1054 · Filter by author canxin121 opened on Nov 2, 2026

• A32 MCRR to an unallocated CP15 64-bit register does not raise Undefined

  renode/renode#1053 · Filter by author canxin121 opened on Nov 2, 2026

• Renode AArch32 VMAX/VMIN return a numeric operand when an input is NaN

  renode/renode#1052 · Filter by author canxin121 opened on Nov 2, 2026