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hexagon: pack Q8_0 files for the NPU and measure them on the IQ-10 - #83
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scripts/quantize_gguf.py gains three flags: - --pad-m32 zero-pads FFN widths that are not a multiple of 32 in the file. The HMX takes no other width for a packed weight, and the loader pads an FFN at load only when its weights are float. - --dit also packs the DiT's weight matrices, except adaLN and the time embedding. - --keep-float REGEX leaves the matching weights at their source precision. tests/py/test_converters.py covers them. docs/benchmark/qualcomm-iq10.md reports latency, memory and fidelity of each Q8_0 configuration of the 13 models on the IQ-10's Hexagon NPU, against the CPU-only build at F32. The runtime is unchanged.
Its F16 rows gave the size of the shipped file, which stores F32 or BF16, so they did not compare with the Q8_0 rows; System RAM is the memory measure. The tensor column now says what it counts.
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What
scripts/quantize_gguf.py:--pad-m32zero-pads FFN widths that are not a multiple of 32 in the file (fc1 rows and bias, fc2 columns). The HMX takes no other width for a packed weight, and the loader pads an FFN at load only when its weights are float.--ditalso packs the DiT's weight matrices, except adaLN and the time embedding.--keep-float REGEXleaves the matching weights at their source precision.tests/py/test_converters.py: covers the three flags.docs/benchmark/qualcomm-iq10.md: a "Q8_0 weights" section.docs/backend/hexagon.md: the flags.CHANGELOG.md.Why
A packed weight runs on the HMX only at widths that are multiples of 32, and the DiT and single weights had no switch.
Results on the IQ-10 at
71cdb09, per model:vla-benchlatency of onepredict()under the TEMPLATE protocol (3 warmups, 20 reps, 3 processes).MemAvailablewhile the process ran, the weights mapped for the NPU included.vla_predict_check) and on one LIBERO observation throughvla-server.Configurations,
quantize_gguf.py --type Q8_0plus:--vision--vision --pad-m32--vision --pad-m32 --dit--keep-floatwith n weights left float, from a greedy search on the fixed-input deviation, the served one, or bothOcto-Small
ACT
TurboVLA
VLA-JEPA
GR00T N1.5
SmolVLA
VLA-Adapter
GR00T N1.6
GR00T N1.7
π0.5
π0
OpenVLA-OFT
Evo-1
Verified
-Wall -Wextra(first-party code): no C++ changectestpasses: no C++ changepython3 tests/py/test_converters.pypassesArchs and backends tested: SmolVLA, π0, π0.5, Evo-1, GR00T N1.5 / N1.6 / N1.7, VLA-JEPA, VLA-Adapter, OpenVLA-OFT, Octo-Small, TurboVLA and ACT on the IQ-10's Hexagon NPU, against the CPU-only build (
-DGGML_HEXAGON=OFF,--weight-dtype f32 --flash-attn 0).