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[RFC] RISC-V: initialize floating-point state for new tasks - #1537

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ChrisX101010:fix/riscv-initial-fpu-state-1536
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ChrisX101010:fix/riscv-initial-fpu-state-1536

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@ChrisX101010

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Related to #1536.

New tasks currently start with FS marked Clean but no saved FP image. This change marks their state Initial and initializes FCSR and all 32 FP registers when entering the task. It covers both first-task startup and the normal restore path, while retaining the saved-image restore path for Dirty contexts.

I'm opening this as a draft for feedback on the approach. RV64/FLEN32 scheduler validation still traps, so this branch is not ready to merge.

Validation against ca75944, using Clang 18.1.3, LLD and QEMU 8.2.2 in WSL:

  • All 16 assembly configurations passed: RV32/RV64, FPU disabled/F/D, F+D+V assembly, and timer/non-timer headers.
  • All 12 first-task/restore-entry cases and four negative controls passed.
  • The real-scheduler fixture passed 10 of 12 positive cases and both negative controls. The RV64/F-only yield and timer-preemption cases trapped; RV32 F/D and RV64 D passed.

The entry checks use scheduler stubs. The separate scheduler fixture uses the actual kernel task/list/port code and checks ordinary FP values and task creation after the scheduler starts. Those fixtures are local and are not added to this PR yet. Physical hardware, GCC runtime builds, vector runtime behavior and the full upstream suite have not been tested.

I used Codex to help develop and review the change; I ran the builds and QEMU tests locally. I'd appreciate feedback on the initialization approach and where a focused regression test would best fit.

Mark new FPU contexts Initial and initialize FCSR and FP registers on first-task startup and normal restore entry.

Related to FreeRTOS#1536.

Developed with Codex assistance; local builds and QEMU checks were run by the contributor.
@sonarqubecloud

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